As the techniques relevant to the present invention, reference is made to the following publications:    (1) JP Patent Kokai Publication JP-A-64-73761,    (2) U.S. Pat. No. 6,269,023 B1,    (3) U.S. Pat. No. 5,768,192,    (4) U.S. Pat. No. 6,181,597 B1 and    (5) JP Patent Kohyo Publication JP-P2001-512290A.
A nonvolatile memory of the MONOS (metal-oxide-silicon) structure, having a dielectric film, called an ONO (oxide nitride oxide film), obtained on layering first a silicon dioxide layer, then layering a silicon nitride film on the a silicon dioxide layer and then layering a silicon dioxide layer of silicon nitride film to form a gate insulating film, has been commercialized to take the place of a nonvolatile memory which has a two-layered gate structure comprised of a control gate and a floating gate. The nonvolatile memory of the MONOS structure is able to store data in a charge trapping layer, which is sandwiched between silicon dioxide layers directly below the gate electrode, at two bits per cell. As for details of the writing, reading and erasure of memory cells of an EEPROM (electrically erasable and programmable ROM), having a charge trapping layer and having a storage node of two bits per cell, reference is had to for example the description of the Publication (5). In the Publication (2), there is disclosed a structure having a limiter for limiting the number of hot carriers flowing into the channel in the nonvolatile memory having an ONO film for trapping the electrical charges in a charge trapping area.
The conventional nonvolatile memory cell, having an ONO layer as a gate insulating film, is explained with reference to FIG. 18. FIG. 18 is based on the description of FIG. 2 of the Publication (5), and shows the cross-section of an EEPROM memory cell of the ONO structure. The memory cell includes a gate structure comprised of an electrically non-conductive dielectric film 220, having a charge trapping function, sandwiched between two silicon dioxide layers 218 and 222. These two silicon dioxide layers 218 and 222 operate as insulating films. An electrically conductive gate film 224 is formed over the upper silicon dioxide layer 222. Two separate bits, that is a left side bit 221 and a right side bit 223, are formed in areas of the charge trapping layer 220 spaced apart from each other. The two bits (storage nodes) are read in the opposite direction from the direction in which they were programmed. For example, the right-side bit 223 in the charge trapping layer 220 is programmed by applying a positive program(write) voltage to the gate electrode 224 and to a drain (N+ diffusion region) 216 to ground the source (N+ diffusion region) 214 to cause sufficiently accelerated hot electrons to be injected into a region adjacent to the drain 216 of the charge trapping layer. The reading of stored bits is done by applying the positive voltage to the gate electrode 224 and to the source 214 and by grounding the drain 216, that is in a direction opposite to that for the programming. The programming and reading of the left-side bit 221 are the same as those for the right side bit 223 except that the source and the drain are interchanged with each other as to their respective functions. For erasing the memory cell, an appropriate erasure voltage is applied to the gate electrode 224. For erasing the right-side bit 223 or the left-side bit 221, an erasure voltage is applied to the drain 216 or to the source 214, respectively, to expel the electrons from the charge-trapping layer. By setting the gate voltage and the voltages for the drain and the source, in this manner, two bits may be stored independently on the left and right sides of the charge-trapping layer 220 directly below the gate electrode.
A typical layout of the non-volatile memory of the NOMOS structure is shown in the Publication (4). The layout of this Publication (4) is not fitted to the high integration level(density) because one contact is needed for a two-bit storage node. On the other hand, the Publication (1) shows an EEPROM (electrically programmable ROM) having two polycrystalline silicon(commonly known as polysilicon) layers arranged in a lattice-like pattern. This EEPROM includes a first group of word lines, a second group of word lines, arranged in a spatially intersecting relationship thereto, and a group of bit lines, arranged on the surfaces of the first and second groups of the word lines, in an oblique direction, extending through the surface of the region of the spatial intersection, with the interposition of an interlayer insulating film, and which are connected common to the source and drain regions extending in the oblique direction of the group of the memory cell transistors through vias of the interlayer insulating film. The memory device described in this Publication (1) has a one-bit storage node per gate and is of the double-layer polysilicon gate structure, and hence the manufacturing method of the memory device becomes complicated.